I'm a Systems Engineering student at the University of Guelph (graduating April 2026), specializing in the intersection of hardware design and software development.
I work at every layer of the stack — from designing CMOS circuits at the transistor level in Cadence Virtuoso to implementing FPGA SoC systems in VHDL/Verilog to building enterprise apps in C# and ASP.NET.
Currently a Software/Systems Developer at ECNG Energy Group, modernizing legacy systems and building automation pipelines. Previously a Teaching Assistant, Robotics Instructor, and VEX Robotics coach.
I love engineering problems that live at the boundary of hardware and software — where the logic meets the physics. Originally from Damascus, Syria 🇸🇾, now building things in Canada 🇨🇦.
Designed a fully functional 8-bit Program Counter at the transistor level in Cadence Virtuoso. Built three sub-modules from scratch: a CMOS transmission gate MUX, a mirror adder ripple-carry full adder, and a master-slave D flip-flop register. Verified via full Spectre transient simulation.
Designed a 128-bit AES encryption coprocessor in Verilog on an FPGA SoC. Built a custom APB IP module in Platform Designer, implemented all AES transformations (SubBytes, ShiftRows, MixColumns, AddRoundKey), key expansion logic, and memory-mapped registers. Validated against NIST test vectors.
Designed a custom synchronous CPU at the RTL level in VHDL targeting FPGA. Architected a multi-stage datapath with register file, ALU, control unit, and memory interface. Developed FSM-based control logic managing fetch/decode/execute/write-back. Debugged in ModelSim, synthesized in Vivado.
Designed a hardware accelerator kernel in C/C++ for FPGA using Vivado HLS on a Xilinx Zynq SoC. Applied loop pipelining, unrolling, and dataflow architectures. Optimized memory via array partitioning. Analyzed HLS reports for clock, latency, II, and BRAM/DSP/LUT utilization.
Complete ARINC 429 Tx/Rx in VHDL on a Nexys A7 FPGA. Implemented 32-bit ARINC word formatting with label, SDI, SSM fields and odd parity. FSM receiver handles bit timing, word detection, and parity validation. Optimized in Vivado for minimal LUT/FF utilization.
Capstone: modified a Creality 3D printer to print directly from raw polymer, eliminating filament. Replaced control board with STM32-based SKR Mini E3, configured/modified Marlin firmware, tuned extrusion rate, temperature profiles, and motion synchronization. Enables recycled-plastic printing.
📄 View Design Day PosterReal-time firmware in C using FreeRTOS on ARM. Task-based architecture for temperature sensing (ADC), control computation, actuator output, and system monitoring. Used queues and semaphores for deterministic inter-task data flow. Validated with oscilloscope-based timing analysis.
Wearable real-time obstacle detection for visually impaired users. Chest-mounted oscillating 2D LiDAR achieves effective 3D sensing. Cane-mounted rotary encoder detects traction loss. Directional haptic motors provide low-latency tactile alerts. Battery life ~12hr. Compliant with Accessible Canada Act.
Modeled and controlled a nonlinear magnetic levitation system. Derived equations from first principles, linearized the model, and designed hierarchical PI (inner current loop) + PID+feedforward (outer position loop) control. Validated in Simulink simulations and validated on real hardware via QUARC.
Designed an agent-based Sugarscape simulation studying how macronutrient distributions impact long-term fat loss. Modeled BMR, caloric deficit, and body-fat dynamics. Identified a stable optimal macronutrient ratio (~40/39/21) validated against real nutritional guidelines across thousands of simulation time steps.
Contributed features to the open-source Glances monitoring tool. Extracted and documented UML architecture, implemented NVMe-specific metrics (temperature, health status, performance tracking), added file system descriptions, and optimized metric displays. Managed sprints via JIRA, version control via GitHub, with comprehensive automated test suites.
Whether you're looking to collaborate on a hardware project, discuss embedded systems, or explore opportunities — I'd love to hear from you.